1. Field of the Invention
The present invention relates to a semiconductor device, and, in particular, to a semiconductor device having element isolation regions and a trench structure formed on the main surface of a semiconductor substrate.
2. Description of the Prior Art
The technology of a circuit isolation element region is one important technology in the fabrication of semiconductor devices. As the trend to large scale integration and miniaturization of semiconductor devices advances, the isolation of semiconductor circuit elements is becoming more and more difficult. In order to increase the degree of integration, the method of shrinking the dimensions for circuit element isolation is an important topic, and is limited to the conventionally known LOCal Oxidation of Silicon (LOCOS) method. In order to overcome this limitation, a trench embedding element isolation structure (hereinafter, referred to as embedded element isolation) has been proposed wherein narrow openings and deep grooves (trenches) are formed in the main surface of the semiconductor substrate and SiO.sub.2 or SiO.sub.2 and polysilicon are embedded in these trenches. With this structure it is possible to maintain the distance between the elements in the direction of depth and to reduce the punch-through problem and the parasitic MOS transistor influence.
The fabricating process for embedded element isolation in a semiconductor device made by conventional technology and the structure will now be explained with reference to FIGS. 1A to 1E.
First, as shown in FIG. 1A, a thin oxidized film 2 is formed on the main surface of a P-type silicon semiconductor substrate 1 by a thermal oxidation method, and an Si.sub.3 N.sub.4 film is formed as an insulating film 3 on the oxidized film 2.
Next, a photoresist film (omitted from the drawing) is formed as a mask by using a photolithographic etching method, and then the Si.sub.3 N.sub.4 film 3 and the oxidized film 2 is selectively removed by means of RIE (Reactive Ion Etching), which become a part of element isolating regions later.
Then, as shown in FIG. 1B, the Si.sub.3 N.sub.4 film 3 which has been selectively etched in this manner above and on which a specified pattern is formed, is used as a mask and a plurality of trenches 4 of specified widths W1, W2, and W3, and a specified depth D1 are formed on the underlying semiconductor substrate 1 by anisotropic etching such as RIE or the like. At this time the trenches 4 have a uniform depth D1 unrelated to the element isolation widths W1, W2, and W3.
Next, as shown in FIG. 1C, the semiconductor substrate 1 is thermally oxidized so that an oxidized film 5 is formed on the exposed inside walls of the trenches 4.
Next, P-type impurities are ion-implanted on the inner section of each trench 4 so that a diffusion region of a comparatively high concentration of P-type impurities of the same type of conductivity as the semiconductor substrate 1 is formed as a channel stopper region 6 on at least the bottom surface of the trench 4.
The channel stopper region 6 is provided to restrain punch-through phenomenon and a parasitic MOS transistor reversal within an N-type impurity diffusion region formed in the semiconductor substrate 1.
An insulating film 7 of SiO.sub.2 is formed over the resulting surface to a thickness almost equivalent to the depth D2 of the trench 4, using Chemical Vapor Deposition (CVD).
Etchback is then carried out on the insulating film 7. Specifically, as shown in FIG. 1D, the SiO.sub.2 insulating film 7 is etched flat from its upper portion, using mechanical abrasion or RIE or the like, until the Si.sub.3 N.sub.4 insulating film 3 is exposed to form a structure wherein the SiO.sub.2 insulating film 7 is embedded in the trench 4.
The accumulated thickness of the insulating film 7 is almost equivalent to the depth D2 of the trench 4 from the main surface of the semiconductor substrate 1. If the accumulated thickness is less than the depth D2 of the trench 4, the insulating film 7 does not reach as far as the edge of the trench 4 in the region where the trench 4 having the width W3 is wide, formed from the right of the drawing, therefore the insulating film 7 cannot completely cover the inside of the trench 4. The etching conditions for the Si.sub.3 N.sub.4 insulating film 3 are selected so that the Si.sub.3 N.sub.4 insulating film 3 acts as a self-adjusting stopper for the etching of the SiO.sub.2 insulating film 7.
Next, as illustrated in FIG. 1E, the Si.sub.3 N.sub.4 insulating film 3 is removed by chemical dry etching (CDE), then the thin oxidized film 2 under the Si.sub.3 N.sub.4 insulating film 3 is removed using a hydrofluoric acid-related solvent so that the main surface of the semiconductor substrate 1 is exposed.
Part of the exposed surface of the semiconductor substrate 1 is used as element regions, and elements such as MOS transistors and the like are formed in these element regions in the conventional technology.
In FIG. 1E, for example, an impurity diffusion region 8 with a conductivity of a type which is the reverse of that of the semiconductor substrate 1 is formed on the exposed surface region of the main surface of the semiconductor substrate 1 using the ion-implantation method.
An element such as a MOS transistor or the like making up an integrated circuit such as a memory or logic or the like is formed here.
As explained above, with the construction of a conventional embedded element isolation region made by filling insulating film into trench formed on the surface of a semiconductor substrate, the depth of the trench from the surface of the semiconductor substrate is uniform, bearing no relation to the element isolation width. This depth is the same as the depth required in the minimum element isolation width wherein it is difficult to ensure the element isolation characteristics.
In addition, the minimum element isolation region having the width of 0.5 .mu.m or less formed on a channel stopper 6 having a normal concentration of an impurities in the semiconductor substrate 1, the punch-through voltage in an impurity diffusion region with a conductivity which is the reverse of that of the substrate which forms the semiconductor substrate is less than the reverse voltage of a parasitic MOS transistor created in the impurity diffusion region with a conductivity which is the reverse of that of the substrate in this semiconductor substrate, therefore it is restricted by this punch-through voltage.
Specifically, in a region where the element isolation width is small, the least depth which can withstand the punch-through voltage must be ensured. In this region, if the trench is shallower than this least depth, the punch-through is not withstood, but at this least depth or deeper, the punch-through is adequately withstood.
On the other hand, as the result of every part of the trench having the same depth, this depth is greater than necessary in a region where the element isolation width is large and bears no relation to the element isolation characteristics, therefore there is a problem with the strength of the substrate. In addition, because of the necessity of embedding the insulating material in a level manner in the trench unrelated to the element isolation characteristics of this region, the formed film of embedded material must be thicker than necessary, even in regions where the trench is not required to be deep. Therefore, the amount of etching for the levelling process in the subsequent processing of the embedded material is unnecessarily increased so that the time to carry out the series of processes is increased and the machining precision is poor.
Because the thickness of the insulating film formed from the embedded material must be greater than necessary in a region with wide element isolation, the film thickness of the embedded material formed on the semiconductor substrate surface must at least be thicker than the depth of the trench after the trench is formed, in order to form a flat surface of the element isolation region on the semiconductor substrate adjacent to the region with wide element isolation and the material embedded in the last element isolation region.